As a technology studied by the inventor of the present invention, for example, the following technology is conceivable for a semiconductor device including a phase change memory. A memory element uses a chalcogenide materials (or a phase change material) containing at least antimony (Sb) and tellurium (Te) such as a Ge—Sb—Te-based one, an Ag—In—Sb—Te-based one as a material of storage layers. A diode is used for a selection device. Characteristics of the phase change memory using the chalcogenide material and the diodes in this manner are described, for example, in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, USA, 2007, p. 472-473 and 616 (Non-Patent Document 1).
FIG. 2 is a diagram showing a relation between pulse widths and temperatures required for phase change of a resistive memory element using a phase change material. When memory information ‘0’ is to be written to this memory element, as shown in FIG. 2, a reset pulse that heats the element to a melting point Ta or more of the chalcogenide material and rapidly cools it is applied. The cooling time t1 is set to be short, for example, about 1 ns; as a result, the chalcogenide material is caused to be in a high-resistance amorphous (non-crystalline) state.
On the other hand, when memory information ‘1’ is to be written, a set pulse that maintains the memory element in a temperature region lower than the melting point Ta and higher than a crystallization temperature Tx that is equal to or higher than a glass transition point is applied; as a result, the chalcogenide material is caused to be in a low-resistance polycrystalline state. Time t2 required for crystallization is different depending on the composition of the chalcogenide material. The temperature of the element shown in FIG. 2 is dependent on Joule heat generated by the memory element itself and the thermal diffusion to the periphery.
In Japanese Patent Application Laid-Open Publication No. 2003-060171 (Patent Document 1), memory cell characteristics and reading conditions of a semiconductor memory device having an array structure in which memory cells having ferroelectric layers are stacked interposing insulating layers are described. Specifically, since the thermal history of the memory cells is different in each layer, differences in the electrical characteristics of the memory cells are generated depending on the formed layers. In order to reliably read such memory cells, a method of changing a reference voltage according to the layer having the accessed memory cell is taught. Japanese Patent Application Laid-Open Publication No. 2007-501519 (Patent Document 2) describes memory cell characteristics of a semiconductor memory device having an array structure in which memory cells comprising a chalcogenide material are stacked. More specifically, it is described that the chalcogenide material has characteristics prone to be affected by formation steps of the stacked arrangement. Japanese Patent Application Laid-Open Publication No. 2004-266220 (Patent Document 3) describes a memory array structure of a stacked-type magnetic memory. Specifically, a method of changing the wiring structure, contact structure, etc. for each layer in order to prevent the writing characteristics from differing in each layer is described.